Design of an IC chip, including its architecture, is a very complex, expensive, and time-consuming task, making verification of that design before fabrication critical. When designing increasingly complex processors or Integrated Circuit (IC) chips such as Application-Specific ICs (ASICs) and system-on-chips (SoC's), functional verification of the design has proven to be a major bottleneck in achieving time-to-market goals. Verification of the design of a complex system such as an IC chip is an iterative process where the entire system (or at least ail of its major features) is tested on a continuous basis for the duration of the design. As the design complexity increases, so does the state space and the number of functional states and finite state machines that need to be verified. In a typical microprocessor design environment, billions of simulation cycles are required to verify all features of the design. Design teams report that functional verification of medium- to large-complexity processors, ASICs or SOC's may consume over 70% of the project's manpower, schedule and budget. In spite of the time and resources consumed by functional verification, it is still often incomplete, allowing design bugs to go undetected.
The design process for an IC chip starts with the creation of a functional specification for the design. Once the functional specification has been completed, the verification team typically creates a test plan that specifies the design features and functions to be tested at both the block and system levels. The verification team then creates testbenches (also known as tests) such as deterministic tests and tests automatically generated to verify design functionality until all test plan requirements have been met. The process of verifying the functional specification is called functional verification, which encompasses the development and implementation of this test plan.
Functional verification ensures functional conformance of an integrated circuit design to its architectural and microarchitectural specifications and determines whether a design is logically correct. The verification process involves developing and simulating tests that are used to determine whether design components (e.g., processor units, resources, functions, etc.) behave according to their functional specification. Functional verification is typically completed before fabrication of the processor, as finding and fixing errors, or bugs, after fabrication proves to be time-consuming and expensive.
To manage the verification of today's complex designs and to be responsive to frequent design specification changes and upgrades, an efficient, iterative process that may be used throughout the duration of the design is desired. To alleviate the burden of frequent design specification changes and upgrades, regression testing is often adopted. Regression testing involves the repetitive testing of a design's major features to ensure changes and upgrades to the design have not introduced new bugs into the system. Verification is a major component of the design process and efficient management of its tasks and resources are important in reducing the number of design iterations and optimizing the length of each iteration. Improved functional verification can cut costs, improve design quality and accelerate time-to-market. In addition, improved functional verification enables companies to sharply increase the productivity of their precious resource, verification personnel.
Different methods have been developed to improve the quality and efficiency of functional verification. These methods include formal verification methods and Assertion-based verification (ABV) methods. Using formal verification methods, testers design tests and run simulations against a compiled model of the design to exercise the tests and to identify any deviations from the formal specification or rules. Some verification tools can generate a set of assertions such as checkers and monitors from the formal rules which can then be used to facilitate the simulation-based verification. In contrast, ABV often relies on arbitrary or non-test plan based factors instead of formal rules. Design and verification engineers define assertions such as checkers and monitors that define verification targets such as design features that need to be verified or critical sequences of operations to be monitored.
Current ABV tools and methods provide mechanisms for designers to define assertions in one or more commonly used languages (e.g., PSL, Verilog, VHDL, C, e, etc.). These assertions are then folded into the verification test bench manually by a designer and exercised during verification. The designer then reviews the simulation output to determine if the assertions worked properly. The verification bottleneck of traditional simulation-based verification (including test generation, simulation, and coverage analysis) has thus been shifted but not eliminated. Defining assertions, ensuring their completeness and accuracy, and maintaining a large number of assertions throughout the architectural and specification changes have proven to be the new verification bottleneck.
Some Electronic Design Automation (EDA) companies (e.g., Mentor Graphics Corporation's 0-in business unit, Cadence Design Systems Inc., etc.) have attempted to make ABV more efficient by providing static design analysis tools and checkerware libraries. These tools, however, do not provide a mechanism for the user to customize the checker libraries during the verification process. These tools also generally require manual generation of assertions, a resource-intensive process. Any assertions generated by these tools are primitive assertions with no visibility to the designer and may only be used within the black-box environment of the tool. Other tools require designers to manually define and maintain verification assertions, requiring significant user effort and time.
There is, therefore, a need for an effective and efficient system to manage Assertion-based verification. There is an even greater need for such a system as the complexity of designs to be functionally verified continues to increase.